1. Technical Field
The present invention relates to cache memories in general, and in particular to set-associative cache memories. Still more particularly, the present invention relates to a set-associative cache memory having a built-in set prediction array.
2. Description of the Prior Art
In order to increase the speed of access to data stored within a system memory, modern data processing systems generally maintain the most recently used data in a high-speed memory known as a cache memory. This cache memory has multiple cache lines, with several bytes per cache line for storing information in contiguous addresses within the system memory. In addition, each cache line has an associated tag that typically identifies a partial address of a corresponding page of the system memory. Because the information within each cache line may come from different pages of the system memory, the tag provides a convenient way to identify to which page of the system memory a cache line belongs.
In order to improve cache hit ratio, set-associative cache memories are commonly utilized in most data processing systems. Generally speaking, for a set-associative cache memory, a higher number of sets typically yields a higher hit ratio. However, most set-associative cache memories employ a so-called xe2x80x9clate selectxe2x80x9d scheme that requires all sets within a set-associative cache memory to be activated simultaneously, and a set-select multiplexor to select one of the sets in which the xe2x80x9chitxe2x80x9d cache line resided. Thus, more power will be consumed as the number of sets increases.
One solution to the above-mentioned problem is to use a set prediction scheme. By allowing only one wordline to be activated based on a prediction method to select only one of the many sets, the set prediction scheme saves power and also improves access time. A bit called the most-recently used (MRU) bit is usually used to predict one of the sets. The MRU bit typically requires to access a translation lookaside buffer (TLB) before the MRU bit can be sent from the TLB to the memory array of the cache memory. The access path to the TLB is known to be one of critical paths for cache accesses such that additional cycles are commonly required. However, because of its relatively large size, the TLB usually cannot be placed at close proximity to the memory array. As a result, the total cache access time of a set-associative cache memory increases with the sizes of its TLB and memory arrays. Consequently, it would be desirable to provide an improved set-associative cache memory with fast access time and yet low power consumption.
In accordance with a preferred embodiment of the present invention, a cache memory can be accessed via an effective address having a tag field, a line index field, and a byte field. The cache memory includes a directory, a memory array, a translation lookaside buffer, and a set prediction array. The memory array is associated with the directory such that each tag entry within the directory corresponds to a cache line within the memory array. In response to a cache access by an effective address, the translation lookaside buffer determines whether or not the data associated with the effective address is stored within the memory array. The set prediction array is built-in within the memory array such that an access to a line entry within the set prediction array can be performed in a same access cycle as an access to a cache line within the memory array.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.